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Printer Enhancement ASIC
Printer Enhancement ASIC
(Preliminary)
Revision 1.0
-1-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
Printer Enhancement ASIC
1. General Description
The Printer Enhancement ASIC provides state-of-the-art resolution enhancement for text, line art, and photo images for all printing modes including fax. The design gives the Printer Controller designer the ability to add the Enhancement Technology into new or existing designs with minimal effort and cost. The Printer Enhancement ASIC operates on the serial video data stream to enhance the output print quality and minimize design interfacing requirement. Operating on a typical 600 DPI engine and with 200, 300, or 600 DPI source data, the edge enhancement logic determines the additional small fractional dots to be added to fill jaggies so that effective resolution is doubled. Gray scale enhancement also operates on 600x1 bit serial data requiring no additional memory to improve gray scale rendering. An additional breakthrough feature is the ability to accept 1200 DPI source data to render 1200 DPI quality for text and gray scale on a 600 DPI engine. A direct digital copy mode allows a Multi-Function Device to pass 8-bit scanner data directly to the printer for higher quality copying. Internal programmable look-up-tables are provided to optimize print quality for different print engines.
Revision 1.0
-2-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
Printer Enhancement ASIC
2. Features
* * * * * * * Photo Enhancement - 144 Gray Levels in 1-bit Mode - 256 Gray Levels in 8-bit Mode Text & Line Art Edge Enhancement: - Source Data (DPI) = 1/3X, 1/2X, or 1X Engine Resolution 1200 DPI Mode Fax Enhancement for 200 DPI Source Data Digital Copy Modes Multiple Print Engine Support - 300 - 600 DPI Internal Precision Modulator
Revision 1.0
-3-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond
Printer Enhancement ASIC
3 Image Enhancement Module Functions
3.1 Setup Setup requirements consist of programming the control registers and downloading LUT (look_up_table) information into LUT memory. All internal register and memory locations can be read by the host CPU to check status and/or hardware integrity. In addition to the LUT memory and control registers, the Line Store memory can be written and read for testing. The memory map for the control registers and internal memories are: Memory Map Internal LUT (512 x 8) Control Registers (18 x 8) Line Store Memory (8K x 16) From PA[9:0] 000 200 UpperLineStoreAddress[3:0] = 0, PA[8:0] = 000 To PA[9:0] 1FF 2FF UpperLineStoreAddress[3:0] = F, PA[8:0] = 1FF
POWER-UP CONDITIONS: Control Registers are powered up in their inactive state. In order to make any mode operational, specific values must be written to the control registers as well as the LUT's, which will be powered up in a random state. LOOK-UP TABLES: Look-up tables are required to be loaded by the CPU. Final tables will be provided after characterization on a sampling of representative engines. LINE MEMORY SIZE: Line store memory is organized as 8K words. This is segmented by the hardware architecture according to what operating mode is selected.
MODE 600x600x1 300x300x1 200x200x1 200x100x1 1200x1200x1 600x600x8 300x300x8 BUFFERS 8 16 16 16 4 NOT BUFFERED 1
3.2 Margin Offset Control: Control register C contains the 11 bit register that sets the left-hand margin position of the image. The count will reflect the amount of 600dpi positions (1/600 ) from the selected edge of the beam detect (BD) signal, regardless of the mode selected. 3.3 Vertical Margin Control The top of page detection is controlled by fsync_en (frame synch enable - control register A, bit 10) and frame sync, (fsynch). Fsync_en is set by software to begin a page (lsynch s will be ignored until the fsynch signal is received). When fsync_en is high we wait for fsynch to go high and then lsynch clocks will begin counting the vertical margin counter. When the vertical margin counter equals the vertical margin top register, (control register E) data transfer will begin. The vertical margin counter will continue to increment on each hysnc and when it reaches the value set in the vertical margin bottom register, (control register F) data Revision 1.0 -4Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
transfer will terminate for the remainder of the page. The CPU is required to reset fsync_en after it has moved the all of the line data into the PRINTER ENHANCEMENT ASIC chip and allowed it to image that data. (one, two, or three additional lines depending on mode). The CPU will then set fsync_en again to prepare the fsynch logic for the next page synch signal, fsynch. 3.4 Input Ports The data input is parallel, eight bit. Data is transferred into the design on the rising edge of the parallel video clock. The first clock after the hysnc signal will transfer the first eignt bits of data into the design. 3.5 Look-Up Table Memory (LUT): To Load or Read the LUT memory the following bit in control register A must be set: CPU2InternalLUT = Load LUT Memory (512x8) Subsequent reading or writing to memory locations 0000-01FF will address the LUT memory, Data Bit 0 = LUT Bit 0. What are LUT's for? Look-up tables translate the fixed image values that are affected by engine linearity, temperature, aging, environmental, toner exhaustion, and other variables as well as features such as toner saver, paper type, type of input, etc. into values that will reproduce the highest quality image possible. The number of variables that influence the printed image are numerous and in order to correctly image the job these variables have to be compensated for. This is the job of the LUT memory.. 3.6 OPERATING MODES 3.6.1 1200x1200x1 1200 Mode is selected by programming control register A bits [3:0] with a 1010. Source data must be in the two line format that can be used. The two line format requires that two lines of 1200 data must be transferred for each hysnc received by the design. The design will transfer two lines of sequential 1200 data per hysnc. The length of the lines is tracked via the line length register value (control register D, [11:0]) and when it reaches the programmed count it repeats the count for the second line. The CPU must program the line length (control register D) with the length of a single line of 1200 data into the Image Enhancement module. To set up the PRINTER ENHANCEMENT ASIC for 1200 Enhanced the LUT memory must be loaded and the following control registers must be programmed: Control Register A Mode Mfunction (see table 2.0) vidkill bdedge (0 = rising edge, 1 = falling edge) vidpol (0 = normal, 1 = inverse) fsync_en (see paragraph for operational desc) Unused Other Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Line Synch Width Register D: Line Length Register Revision 1.0 -5BITS [3:0] [6:5} 7 8 9 10 [12:11] 4, 13, 14, 15 BITS [15:0] BITS [10:0] [15:11} [11:0] VALUE 1010 XX 1 0 or 1 0 or 1 0 or 1 00 0,0,0,0 VALUE 00h VALUE 0 - 3FFh 0 - 1Fh 0 - FFFh
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register [15:12] [15:0] [15:0] 0000 0 - FFFFh 0 - FFFFh
3.6.2 600x600x1 600 Mode is selected by programming control register A,bits [3:0]. There are four different 600x1 operating modes to choose from. 0h is selected for enhanced text only, 1h is the test mode for 0h. 2h is for enhanced text and enhanced one bit gray scale. 3h is for unenhanced text and enhanced one bit gray scale. The CPU must program the line length (Control Register D) of a single line of 300 data into the Winbond chip. To set up the Winbond chip for 600 Enhanced the LUT memory must be loaded and the following control registers must be programmed: Control Register A Mode Mfunction (see table 2.0) vidkill bdedge (0 = rising edge, 1 = falling edge) vidpol (0 = normal, 1 = inverse) fsync_en (see paragraph for operational desc) Unused Other Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Unused D: Line Length Register D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register BITS [3:0] [6:5} 7 8 9 10 [12:11] 4, 13, 14, 15 BITS [15:0] BITS [10:0] [15:11} [10:0] [15:12] [15:0] [15:0] VALUE 0h, 1h, 2, 3h 00 1 0 or 1 0 or 1 0 or 1 00 0,0,0,0 VALUE 00h VALUE 0 - 3FFh 00000 0 - 3FFh 0000 0 - FFFFh 0 - FFFFh
3.6.3 300x300x1 300 Mode is selected by programming control register A bits [3:0]. There are two different 300x1 operating modes to choose from. 4h is selected for enhanced text only, 5h is the test mode for 4h. To set up the PRINTER ENHANCEMENT ASIC chip for 300 Enhanced the LUT memory must be loaded and the following control registers must be programmed: Control Register A Mode Mfunction (see table 2.0) vidkill bdedge (0 = rising edge, 1 = falling edge) vidpol (0 = normal, 1 = inverse) fsync_en (see paragraph for operational desc) Unused BITS [3:0] [6:5} 7 8 9 10 [12:11] VALUE 4h, 5h 00 1 0 or 1 0 or 1 0 or 1 00
Revision 1.0
-6-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
Other Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Unused D: Line Length Register D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register 4, 13, 14, 15 BITS [15:0] BITS [10:0] [15:11} [10:0] [15:12] [15:0] [15:0] 0,0,0,0 VALUE 00h VALUE 0 - 3FFh 00000 0 - 3FFh 0000 0 - FFFFh 0 - FFFFh
3.6.4 200xNx1 200 Mode is selected by programming control register A bits [3:0]. There are four different 200x1 operating modes to choose from. 6h is selected for enhanced text only, 7h is the test mode for 6h. 8h is selected for 200x100x1 enhanced text. 9h is the test mode for 8h. To set up the Winbond chip for 200 Enhanced the LUT memory must be loaded and the following control registers must be programmed: Control Register A Mode Mfunction (see table 2.0) vidkill bdedge (0 = rising edge, 1 = falling edge) vidpol (0 = normal, 1 = inverse) fsync_en (see paragraph for operational desc) Unused Other Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Unused D: Line Length Register D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register BITS [3:0] [6:5} 7 8 9 10 [12:11] 4, 13, 14, 15 BITS [15:0] BITS [10:0] [15:11} [10:0] [15:12] [15:0] [15:0] VALUE 6h, 7h, 8h, 9h 00 1 0 or 1 0 or 1 0 or 1 00 0,0,0,0 VALUE 00h VALUE 0 - 3FFh 00000 0 - 3FFh 0000 0 - FFFFh 0 - FFFFh
3.6.5 600x600x8 600x8 Mode is selected by programming control register A bits [3:0]. To set up the PRINTER ENHANCEMENT ASIC chip for 600x8 the LUT memory must be loaded and the following control registers must be programmed: Control Register A Mode Mfunction (see table 2.0) vidkill Revision 1.0 -7BITS [3:0] [6:5} 7 VALUE Bh 00 1
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
bdedge (0 = rising edge, 1 = falling edge) vidpol (0 = normal, 1 = inverse) fsync_en (see paragraph for operational desc) Unused Other Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Unused D: Line Length Register D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register 8 9 10 [12:11] 4, 13, 14, 15 BITS [15:0] BITS [10:0] [15:11} [10:0] [15:12] [15:0] [15:0] 0 or 1 0 or 1 0 or 1 00 0,0,0,0 VALUE 00h VALUE 0 - 3FFh 00000 0 - 3FFh 0000 0 - FFFFh 0 - FFFFh
3.6.6 300x300x8 300x8 Mode is selected by programming control register A bits [3:0]. The CPU must program the line length (Control Register D ) of a single line of 300 data into the Winbond chip. To set up the Winbond chip for 300x8 Enhanced the LUT memory must be loaded and the following control registers must be programmed: BITS VALUE Control Register A Mode [3:0] Ch [6:5} 00 Mfunction (see table 2.0) vidkill 7 1 bdedge (0 = rising edge, 1 = falling edge) 8 0 or 1 vidpol (0 = normal, 1 = inverse) 9 0 or 1 fsync_en (see paragraph for operational desc) 10 0 or 1 Unused [12:11] 00 Other 4, 13, 14, 15 0,0,0,0 Control Register B Unused Other Control Registers C: Horizontal Margin Register C: Unused D: Line Length Register D: Unused E: Vertical Margin (Top) Register F: Vertical Margin (Bottom) Register BITS [15:0] BITS [10:0] [15:11} [10:0] [15:12] [15:0] [15:0] VALUE 00h VALUE 0 - 3FFh 00000 0 - 3FFh 0000 0 - FFFFh 0 - FFFFh
3.6.7 ONE BIT (600/300/200) TEST MODES Test modes are different from normal one bit modes in that they bypass the Edge Enhancement Unit, (EEU). The input data is sampled just prior to the LUT memories. Selecting 600x600x1t, 600x600x1tg, 300x300x1t, 200x200x1t, or 200x100x1t one bit modes in register A will operate this way. The purpose of the test mode is to be able to bypass the EEU logic and
Revision 1.0
-8-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
present the assembled data directly to the modulator in order to isolate faults. Output will appear exactly like the input bit map.
Revision 1.0
-9-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
4. Image Enhancement Module Registers
Memory Map Internal LUT Control Register From PA[9:0] 000 200 To PA[9:0] 1FF 2FF
Control Register A (address= 201, 200) 15(MSB) Enable CPU to access line store memory CPU2LineStore 14 Control bit foe 300x150 or 600x300 screen Screen150 13 Enable CPU to access internal LUT CPU2InternalLUT 12 00: 8-bit parallel video data in, SourceSelect 1 11 11: serial video data in SourceSelect 0 10 Page start detection control bit. Must goes low after a page to fsync_n reset circuit that looks for page start 9 video polarity, vidpol XOR (video AND vidkill) vidpol 8 line sync edge sensitivity bdedge 7 Drive video kill output, 0: kill video output vidkill 6 Drive black output black 5 Drive force output force 4 1: 16-bit line store, 0: 8-bit line store LineStore16_8n 3 mode control bit 3 2 mode control bit 2 1 mode control bit 1 0 mode control bit 0 Mode Control Bit Table Mode m600x1e m600x1t m600x1eg m600x1tg m300x1e m300x1t m200x1e m200x1t m100x1e m100x1t m1200x1 m600x8 m300x8 mode control bit [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Description Mode 600x1 test Mode 600x1 enhanced with 1-bit grayscale Mode 600x1 not edge enhanced, just 1-bit gray scale Mode 300x1 enhanced Mode 300x1 test Mode 200x1 enhanced Mode 200x1 test Mode 100x2 enhanced Mode 100x1 test Mode 1200x1 Mode 600x8 Mode 300x8
Control Register B (Address = 203, 202) 15 - 11 reserved 10 Alignment bit 2 9 Alignment bit 1 8 Alignment bit 0
Select shift register which data to use for serial data in
Revision 1.0
-10-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
7-5 4 1 0 reserved ShiftDir ClockSelect 1 ClockSelect 0 Direction to shift 1-bit data, 1:LSB first, 0:MSB first
Control Register C (Address = 205, 204) 15 - 11 Number of clocks in CPUlsync LsyncWidth 10 - 0 Count of engine clocks to delay the start of the line HMargin
15 -12 11 - 0
Control Register D (Address = 207, 206) reserved Number on source pixels in line LineLength
15 - 0
Control Register E (Address = 209, 208) Vertical margin in lines VMarginTop
15 - 0
Control Register F (Address = 20B, 20A) VMarginBottom
15 - 0
Control Register G (Address = 20D, 20C) C register for modulator, default = 0xb c_reg[15:0] c_adj[15:0] = c_reg[15:0] window_adj = c_reg[14:0]
15 - 4 3-0
Control Register H (Address = 20F, 20E) VMarginTop UpperLineStoreAddress [3:0]
line store address(lsma) = { UpperLineStoreAddress[3:0], pa[8:0] }
15 - 0
Control Register I (Address = 211, 210) T register for modulator, default = 7fe1 t_reg[15:0] c_lb = t_reg[0] window_adj_lb = t_reg[1]
Revision 1.0
-11-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
5. Pin Description
NAME lsmd[15:0] TYPE B Pin Number 97, 96, 95, 94, 93, 92, 90, 89, 88, 86, 85, 84, 82, 81, 80, 79 15, 14, 12, 11,10, 9, 8, 7, 5, 4, 1, 100, 99 75 91 78 27, 23, 22, 21, 20, 19, 18, 16 29 Description Bidirection 16-bit line memory data.
lsma[12:0] lsmdoe_n lsmwe_n lsmcs1_n pvideo[7:0] rst_n
O O O O I I
13-bit address for line memory address. Active low line memory data output enable. Active low line memory write strobe. Active low line memory chip select. 8-bit parallel video data inputs. Active low reset. rst_n reset all control registse except - register G = 000B - register I = 7FE1
pvclk svideo svclk
O I O
31 33 32
Parallel video strob clock output. pvideo is to be latched into superchip on the rising edge of pvclk. serial video data input Serial video clock. svclk is continuous clock output with SourceSelect[1:0] = 00 when fsync_n is set to 1. clocked line sync output Line sync output to processor. The width of sync may be programmable by LsyncWidth in control register C[15:11] Processor data. pmode defins the meaning of pwr_n and prd_n. - pmode[1:0] = 00, prd_n and pwr_n are labelled. - pmode[1:0] = 01, pwr_n become read/write strobe, in this mode prd_n and pwr_n should be tied together.
lsync_n CPUlsync_n
O O
34 35
pd[7:0] pmode[1:0]
B I
45, 44, 43, 42, 40, 39, 38, 37, 46, 47
prd_n pwr_n pcs_n pa[9:0]
I I I I
49 50 51 63, 62, 61, 60, 59, 57, 56, 55, 53, 52
Active low processor read enable. Active low processor write enable. Active low processor chip select. Processor address
Revision 1.0
-12-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
fsync_n BD Video clk vdd gnd N.C. I I O I 64 65 66 68 13, 28, 36, 48, 58, 74, 87, 98 6, 17, 30, 41, 54, 67,76, 77, 83 2, 3, 24, 25, 26, 69, 70, 71, 72, 73 Reserved Active low page start sync input. Raw beam detect input from engine. Video data output to engine. Input x1 clock for video processing. It should fit to engine speed.
Revision 1.0
-13-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
6. Pin Assignment
l s m llc sss mm1 g dd_n 10nd l s m d o ev _d nd f s y V n i c d eB_ oDn
g n d
n . c .
n . c .
n . c .
n . c .
n . c .
c l k
g n d
p a 9
p a 8
p a 7
p a 6
p a 5
v d d
p a 4
p a 3
p a 2
g n d
p a 1
p a 0
p c s _ n
lsmd2 lsmd3 gnd lsmd4 lsmd5 lsmd6 vdd lsmd7 lsmd8 lsmd9 lsmwe_n lsmd10 lsmd11 lsmd12 lsmd13 lsmd14 lsmd15 vdd lsma0 lsma1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 W901R0F 90 41 100-Pin QFP 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
pwr_n prd_n vdd pmode0 pmode1 pd7 pd6 pd5 pd4 gnd pd3 pd2 pd1 pd0 vdd
CPUlsync_n
lsync_n svideo svclk pvclk
l s m a 2
n . c .
n . c .
l s m a 3
lg sn md a 4
l s m a 5
l s m a 6
l s m a 7
l s m a 8
l s m a 9
lv sd md a 1 0
l s m a 1 1
l s m a 1 2
p v i d e o 0
g n d
p v i d e o 1
p v i d e o 2
p v i d e o 3
p v i d e o 4
p v i d e o 5
p v i d e o 6
n . c .
n . c .
n . c .
p v i d e o 7
v d d
r s t _ n
g n d
Revision 1.0
-14-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Printer Enhancement ASIC
CORPORATE HEADQUARTERS: NO. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan, R.O.C. TEL: 886-3-5770066 FAX: 886-3-5792646
INFORMATION CONTACTS: Rongken Yang Visual Comm. Product Design Dept. I TEL: 886-3-5796142 E-mail: rkyang@winbond.com.tw
Note: All data and specifications are subject to change without notice.
Revision 1.0
-15-
Publication Release Date: 10/07/97
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.

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